General-purpose processors remain essential. But as AI workloads grow larger, more power-constrained, and more specialized, they are increasingly no longer being asked to do everything. This @eetimes article by Scott Seal makes a clear case for why custom silicon has moved from a specialized option to a core part of data center architecture, covering five dimensions where purpose-built hardware changes the equation: workload optimization, performance per watt, latency reduction, data movement efficiency, and long-term economics at scale. For data center architects, the question is shifting from which processor is fastest to which parts of the workload are important enough to optimize in silicon. Read the full article: mrvl.co/474wstb

OCP Global Summit 2026 was a defining moment for open AI infrastructure, and Marvell was at the center of it. Nine product demonstrations, 14 speaking sessions, and a landmark announcement with Microsoft and Oracle to advance an open security standard for data centers. The week also brought two major product announcements: second-generation Structera X CXL memory expanders with industry-first six-channel DDR4 and DDR5 support, and new Alaska A and Alaska E connectivity solutions advancing AI scale-up networks to 224G per lane.

Marvell Senior Vice President and General Manager of the Photonic Fabric Business Unit Preet Virk will deliver a keynote at the ISIG Executive Summit SEA in Penang, Malaysia, presenting in the Emerging Technology session focused on silicon photonics, co-packaged optics, and compound semiconductors. ISIG brings together senior executives and decision-makers from across the global semiconductor ecosystem, making it a fitting stage for a conversation about the technology transitions reshaping AI infrastructure connectivity. Learn more: mrvl.co/4s5W5Ua

HBM stacks today sit 1.5 millimeters from a GPU. What if they didn’t have to? In this clip from a recent conversation with @theCUBE, Marvell Executive Vice President and General Manager of Data Center Networking Dave Lazovsky walks through the Photonic Fabric Memory Module, the first optically interconnected high-capacity, high-bandwidth memory solution, capable of delivering up to 32 terabytes of disaggregated memory capacity up to 50 meters away from compute. For the first time, memory capacity can scale independently from compute. Watch the full interview: mrvl.co/4s5SC86

Silicon photonics is becoming foundational to scaling AI. At The Six Five Summit, @MarvellTech CEO Matt Murphy discussed the shift from DSP-based optics to CPO and NPO, and how Inphi and Celestial AI strengthen Marvell’s next-gen AI connectivity portfolio. $MRVL

Focus compounds. With 75 to 90% of revenue coming from the data center, Marvell invests its R&D entirely around that application, building foundational technology like SerDes that carries across the full product portfolio. In this clip from a recent @theCUBE conversation, Marvell Executive Vice President and General Manager of Custom Cloud Solutions Will Chu explains how that focus drives competitive advantage and keeps the flywheel going. Watch the full interview: mrvl.co/3TDXnJg

Marvell arrived at the @OpenComputePrj Global Summit with the industry's most comprehensive portfolio of open AI infrastructure solutions, and the energy at Booth B31 reflected the momentum driving this market. Across nine product demonstrations, Marvell showcased innovations spanning networking, interconnect, memory, storage, security, and optical connectivity, including the Teralynx T100 102.4T next-generation data center switch, Structera CXL memory solutions, Ara DSP 1.6T transmit-retimed optics, COLORZ 800G ZR/ZR+ with MACsec, active electrical and copper connectivity platforms, the Bravera PCIe 6.0 SSD controller, and an integrated hardware security module. Marvell engineers and executives also led 14 speaking sessions throughout the event. One of the week's highlights was the announcement of a new OCP Working Group formed with Microsoft and Oracle to advance an open security standard for data centers. The conversations at OCP reinforced what we're hearing across the industry: hyperscalers and cloud operators want open, standards-based architectures that deliver both design flexibility and operational efficiency at scale. Marvell is helping make that vision a reality. #OCPSummit26

Good conversation at @MarvellTech Investor Day w/ @DanielnewmanUV, Sandeep Bharathi, Xi Wang, and Russ Esmacher. The part that stood out is how far ahead connectivity has to be planned. Everyone’s arguing copper vs. optics. The answer is both, and the decisions were made before most people started paying attention. $MRVL

At the @OpenComputePrj Global Summit 2026 Innovation Village, Marvell and NXP are demonstrating cross-vendor interoperability for the Open Boot Management Framework Interface Consolidation Protocol, a key OCP specification that standardizes communication between host processors and baseboard management controllers. The live demo shows Marvell IMC processors running an OBMF ICP software stack over USB, supporting a range of sensor interfaces including I2C, I3C, GPIO, UART, and SPI. The OBMF workstream includes major industry participants across the data center ecosystem, reflecting strong momentum toward unified, open out-of-band platform management for AI and cloud infrastructure. The broader significance: as AI data centers grow in scale and complexity, standardized management interfaces reduce deployment complexity, eliminate vendor lock-in, and make large-scale infrastructure easier to operate. Marvell’s leadership in OBMF ICP positions its IMC processor family as a platform for the open, secure management layer that next-generation data centers require.

Skipping a process node is almost unheard of in the semiconductor industry. Marvell did it anyway. In this clip from a recent conversation with @theCUBE, Marvell Executive Vice President and General Manager of Custom Cloud Solutions Will Chu explains the decision made around 2018 and 2019 to jump directly from 16nm to 5nm, bypassing 7nm entirely, and how that commitment to leading-edge process technology, continued through 3nm, 2nm, and 14 angstrom, became the foundation for the company’s growth in cloud and data center infrastructure. Watch the full interview: mrvl.co/3TDXnJg

Security is front and center at the Marvell presence at the @OpenComputePrj Global Summit 2026, including a demonstration at the Microsoft booth showing secure key transfer between a Marvell LiquidSecurity PCIe card and a Microsoft integrated HSM board, both operating within NIST FIPS 140-3 Level 3 boundaries. The demonstration supports a broader initiative: Marvell, @Microsoft, and @Oracle have established a new OCP Working Group to define open specifications for integrated hardware security modules that securely caches and manages cryptographic keys directly at the server level. The goal is to keep keys within a certified hardware boundary, reducing latency and improving scalability while strengthening security for AI and confidential-compute workloads. #OCPSummit26

Marvell has been recognized once again as a Great Place to Work®. This year, Marvell received this honor in a total of seven countries; this is the fourth year in a row for the United States, the third year for India and Vietnam, and the first year for Singapore, Taiwan, Argentina and Israel. This certification is an important milestone to highlight and unite more Marvell employees around the globe, celebrating the community and collaborative environment they foster every day. “A certification doesn’t create a great workplace—it recognizes one,” says Executive Vice President and Chief Human Resources Officer Janice Hall. “The workplace we’re being recognized for is one we all help create every day through the way we work together, support one another and deliver for our customers. Congratulations to our teams across all seven certified countries.” #CertificationNationDay

Today's Marvell presentations at the @OpenComputePrj Global Summit: Integrated HSM: Bringing Silicon-level Key Security to the Server Tray Time: 8:20 AM – 8:40 AM Location: Room 212 Speaker: Craig Barner, Senior Distinguished Engineer Custom HBM as a System: Co-designing the Base Die, Die-to-Die Power, and Package Thermals for AI Accelerators Time: 8:20 AM – 8:40 AM Location: Room 211 Marvell Speaker: Hsin-wei Tseng, Director, Product Management UALink-SAI: A Common Abstraction for Scale-Up AI Switches Time: 10:05 AM – 10:25 AM Location: Room 210AE Speakers: Ayyappa Nuthalapati, Senior Principal Software Architect & Ravindranath Coimbatore Kanakarajan, Distinguished Engineer XPU Composable Smart Memory Fabric Time: 10:50 AM – 11:05 AM Location: Room LL21BC Speaker: Gaurav Agarwal, Senior Distinguished Engineer & Satananda Burla, Distinguished Engineer Secure Key Distribution Protocol for SoC Hardware Blocks Time: 1:15 PM – 1:30 PM Location: Room 212 Speaker: Craig Barner, Senior Distinguished Engineer Learn more about Marvell's OCP presentations: mrvl.co/4d8KOvU #OCPSummit26

KV cache capacity determines time to first token, throughput, and XPU utilization. When memory runs out, performance collapses. The second generation of Marvell Structera X is built to ensure that doesn’t happen. The Structera X 3406 and 3506 are the industry’s first six-channel DDR4/DDR5 CXL memory expansion, featuring 50% more channels than the prior generation. The DDR4 variant supports up to 9TB across 18 RDIMM slots. The DDR5 variant supports up to 6TB across 12 RDIMM slots. Both deliver 256GB/s of host bandwidth via PCIe Gen 6, multi-host sharing across up to four hosts, 5x higher LZ4 compression throughput, and industry-first post-quantum security. Director of Product Marketing, Custom Cloud Solutions, Arifur Rahman details the full architecture and how Gen 2 fits within the broader Marvell end-to-end CXL portfolio: mrvl.co/4yqR9L9

The optical links connecting distributed AI data centers carry mission-critical traffic and are increasingly high-value targets. Traditional approaches bolt on external encryption appliances, adding cost, power, rack space, and complexity. Marvell is demonstrating a different approach at the @OpenComputePrj Global Summit 2026, Booth B31. The industry’s first 800G ZR/ZR+ OSFP pluggable module with native MACsec encryption, powered by a 2nm coherent DSP, delivers wire-speed security at 800G with no external appliances required. Live traffic traverses an encrypted optical link between two modules, with MACsec in real time to prove encryption is active. Security that travels with the optic, at full speed. #OCPSummit26

Marvell is demonstrating its end-to-end connectivity portfolio at the @OpenComputePrj Global Summit 2026, Booth B31, spanning secure optical interconnects, high-speed active electrical cables, and next-generation copper connectivity. The live 800G ZR/ZR+ demonstration shows the industry's first OSFP pluggable module with integrated MACsec encryption, powered by a 2nm coherent DSP and running live in a TL-10 switch. Alongside that, 1.6T active electrical cables and a 1.6T-to-800G gearbox AEC demonstrate how 200G-per-lane infrastructure can be deployed while protecting existing 100G-per-lane investments through breakout and lane-rate conversion in a single cable. A hybrid 200G AEC/ACC Y-cable and a 300G PAM8 active copper cable demonstration round out the display, showing cost-optimized short-reach connectivity and next-generation speeds over existing cable infrastructure. #OCPSummit26

Today's Marvell presentations at the @OpenComputePrj Global Summit: Beyond Scale-out: SONiC's Path to Memory-semantic AI Fabrics Time: 9:05-9:25am Location: Room 230A Speaker: Ravindranath Coimbatore Kanakarajan, Distinguished Engineer Bridging Compute and Memory Fabric: Data Services for Direct XPU Access Time: 12:50-1:05pm Location: Room LL21DE Speaker: Gaurav Agarwal, Senior Distinguished Engineer Plug-and-play ML Pipelines for SONiC: On-Device Intelligence with Advanced Feature Extraction Time: 1:45-2:05pm Location: Room 230A Speaker: Venkata Ravichandra Mynidi, Senior Principal Engineer Frameworks and APIs Alignment for Cross-vendor: direction alignment and gaps, path forward toward a converged API Time: 4:35-5:00pm Location: Room LL21DE Speaker: Gaurav Agarwal, Senior Distinguished Engineer Secure Key Distribution Protocol for SoC Hardware Blocks Time: 1:15 PM – 1:30 PM Location: Room 212 Speaker: Craig Barner, Senior Distinguished Engineer Learn more about Marvell's OCP presentations: mrvl.co/4d8KOvU

Marvell is showcasing the Teralynx T100, the industry’s first monolithic 102 Tbps Ethernet switch purpose-built for AI scale-out networks, at the @OpenComputePrj Global Summit 2026, Booth B31. Demonstrations include a recorded showcase of Congestion Signaling working on the T100, adaptive routing and switching running on a Teralynx 10 fabric connected to real GPU servers processing live ML workloads in partnership with Larch Networks and Dorado Software, and an AI infrastructure modeling tool showing how the T100 functions as an ESUN switch. A virtual rack gives customers and partners a closer look at the different T100 packaging options alongside the Marvell differentiated memory fabric portfolio with CXL. Stop by Booth B31 to see it in action. #OCPSummit26

Memory is increasingly the constraint on compute infrastructure performance. Marvell is demonstrating a range of CXL memory and storage solutions at the @OpenComputePrj Global Summit 2026, Booth B31, including one running in a server from @Meta. Demonstrations include Structera X CXL memory expansion running in Meta's memory-optimized server. Structera A near-memory accelerators are shown powering a 10 billion-scale vector database in a Kubernetes cluster, reducing data movement across the fabric by 60 times. Also on display is the Bravera SC6 PCIe Gen 6 NVMe SSD controller for next-generation enterprise and AI storage workloads. #OCPSummit26

Marvell is demonstrating the industry's first 2nm 400G/lane PAM4 solution at the @OpenComputePrj Global Summit 2026, Booth B31, a technology that enables the transition to 3.2T data center connectivity. The demonstration reflects where the AI infrastructure bottleneck has shifted: from compute, to memory, and now to connectivity. Moving from today's 200G-per-lane architectures to 400G per lane doubles the bandwidth path to 3.2T optical interconnect while improving power efficiency for server-to-switch and switch-to-switch links across AI clusters. #OCPSummit26