ALT Analog in-memory computing delivers efficient neural network inference at the edge, but systems deployed in non-stationary environments may need to adapt in situ to locally acquired data. Backpropagation faces two structural obstacles here. Its global error transport lets stochastic write errors compound across layers, and its backward pass demands bidirectional, high-precision peripheral circuitry absent from inference-oriented crossbar arrays. We introduce Channel-wise Spatial Gradient learning (CwSG), a strictly local, forward-only rule that trains each convolutional layer by rewarding spatial variation in its feature maps. In simulations replaying the measured trajectories of 1,189 phase-change memory and 1,268 filamentary memristor devices, CwSG learns with single, unverified, sub-1 V pulses. It matches backpropagation on phase-change memory with 59-fold fewer pulses and outperforms it by 53 percentage points on highly variable filamentary memristors, with 8-bit forward converters

ALT Neuro-symbolic artificial intelligence (NeSy AI) combines neural perception with symbolic reasoning, enabling logical reasoning. Hyperdimensional computing (HDC) is promising for NeSy AI, owing to its high parallelism and strong robustness to noise. However, the dense neural operations and memory-intensive symbolic inference in NeSy impose a severe "memory wall" bottleneck. Existing NeSy accelerators either focus solely on symbolic kernels or rely on conventional digital architectures, lacking a unified and energy-efficient hardware substrate. Moreover, exploring optimal hardware design configurations often requires costly trial-and-error. In this work, we propose UnO-NeSy, a unified CiM framework for optimizing NeSy computing. UnO-NeSy consists of UnO-CiM, an ultra-low-power NeSy architecture based on a homogeneous 2FeFET–2R compute-in-memory (CiM) array that supports both neural computation and HDC reasoning, and UnO-Sim, a cross-workload, end-to-end CiM simulator that models device

ALT On ranked directed acyclic graphs coupled by vertex conflicts we study exact-arrival multi-agent path finding (departure and arrival pinned in place and time) posed as a distributed output task: every cell must emit its own bit of a valid joint path-support mask. The machines are cellular: one automaton per cell, state factored over cells, communication only along a fixed local fabric, synchronous rounds, a query-independent output round, no central decoder, and a per-topology transition code. "Necessary" here means: on an explicit hard topology, over all its feasible queries, no universally correct local-only architecture can renounce either temporal orientation; with global flags, impossibility becomes a bandwidth-round trade-off. The class is not vacuous: a flooding machine solves every instance in as many rounds as the diameter of the local fabric. The bound survives two concessions: we supply every agent's exact individual cavity, which alone solves the single-agent problem in zer

ALT The growing memory demands of artificial neural networks pose a major challenge for energy-efficient computing, particularly for models that rely on large collections of high-dimensional weight and embedding vectors. Conventional memory architectures store these vectors individually, requiring many memory cells per vector and limiting achievable storage density. Here we demonstrate an analog memory architecture that encodes multiple vectors in a distributed superposition within a single memory array. Individual vectors are recovered through in-memory matrix-vector multiplication, allowing the degree of superposition to be tuned to balance storage density against recall fidelity. This approach introduces a new scaling dimension for analog memory, in which effective storage density can be increased without a corresponding increase in the number of physical memory cells. The distributed representation also provides resilience to device-level noise. We implement the architecture on a proto

ALT Distributing quantum circuits across a network of quantum devices is a recent approach to improve the scalability of quantum computation. Entangled pairs of qubits distributed across network nodes are used as a communication resource for executing inter-node (remote) gates. However, establishing these entanglement pairs incurs significant latency, and doing so during the circuit's execution may lead to the decoherence of logical qubits. Instead, it may be beneficial to distribute certain entanglement pairs before the circuit is executed. Thus, we consider the problem of distributing a quantum circuit across a quantum network containing some pre-distributed entanglement pairs and seek to minimize the execution time of the circuit. We address this problem in three steps. First, given the quantum network and (optionally) a probability distribution over training circuits, we determine a set of pre-distributed entanglement pairs under a specified budget. Second, we compute a qubit-to-memory

ALT Emerging quantum networks enable distributed quantum computing (DQC) by interconnecting modest, noisy quantum processors. However, practical deployments face tight memory budgets, probabilistic entanglement generation, and decoherence, all while serving multiple users. In realistic settings – cloud execution, iterative/interactive workloads and concurrent jobs – circuits do not arrive in a single batch but as a stream. This creates a fundamentally online problem: the system must react to stochastic arrivals, balance latency and throughput, and remain stable under varying loads without foresight of future jobs. We study Online Scheduling and Distribution of Quantum Circuits (OS-DQC) and formalize the online scheduling problem for quantum networks: circuits arrive over time and must be executed without knowledge of future arrivals. At each event time (arrival or completion), the system decides which waiting circuits to launch and how to place their qubits, while accounting for congestion

ALT Molecular communication is a novel paradigm for the design of nanonetworks. It uses molecules as information carriers and enables communication between nanodevices. DNA-based molecular communication is a promising approach for medical applications, such as in-body networks for diagnostics and drug delivery. However, the transition from theoretical models to practical experiments is still in its early stages. This survey reviews experimentally validated DNA-tiles, nanocarriers, and biosensors relevant to implementing DNA-tile-based nanonetworks in vitro. We evaluate these components based on their stability, compatibility, cost-effectiveness, and overall suitability for wet-lab implementation. Based on this analysis, we identify promising component combinations and derive a blueprint for a minimal proof-of-concept experiment. The resulting framework provides researchers with both a structured overview of experimentally relevant design choices and a concrete starting point for implementi

ALT Efficient irrigation management requires timely responses to soil moisture conditions and anticipated weather changes. This article presents an embedded, weather-based irrigation system that integrates soil moisture monitoring using multiple sensors, edge-based decision-making, automated pump control, and local data management. Four capacitive soil moisture sensors are connected to an STM32F103C8T6 microcontroller for data acquisition, while a BTT Pi V1.2 platform evaluates the sensor data, retrieves short-term weather forecasts, makes irrigation decisions, manages a graphical user interface, and stores operational data locally. Individual sensor readings serve as the basis for zone-level irrigation decisions, while the median of four time-averaged readings supports monitoring and analysis. Forecasted precipitation is taken into account as effective precipitation to reduce the calculated irrigation requirement before the pump is activated. The system was evaluated as part of a one-mont

ALT Quantum processors are increasingly used as accelerators inside high-performance computing (HPC) workflows. A workflow runtime decides which quantum circuits to run, how to group them into provider jobs, and what to repeat after a failed attempt. Many search problems split into independent parts, but the runtime can use that structure only when the workflow exposes the parts and a validity check for each one. SemQBench measures what a runtime gains from this visibility. It compares seven execution policies for the same search problem, including two controls without amplitude amplification. The policies change one runtime choice at a time: whether to amplify, whether partial results may be combined across runs, whether the parts share one circuit, and what a retry keeps. We run them on the 20-qubit IQM Garnet processor using 106 distinct circuits in three jobs, and report circuit executions, active device time, and provider jobs separately before combining them in a cost model. Amplifyi

ALT Failures of agricultural machinery are costly when breakdowns occur during narrow work windows and are discovered too late for planned service. Audio-based condition monitoring offers a low-cost retrofit sensing path because operators already treat abnormal sound as an informal diagnostic cue. Whether such systems are adopted, however, depends on how well they fit farm workflows, repair constraints, and stakeholder decision-making. This paper reports a stakeholder discovery study of audio-based condition monitoring for agricultural machinery. We synthesize semi-structured interviews with farm operators, dairy operators, dealership and service personnel, manufacturers, integrators, and domain experts, together with a short survey. Across sources, downtime avoidance emerged as the dominant value driver, and failures were most commonly recognized through unusual noise and loss of functionality. Survey responses further indicate a gap in maintenance visibility and low penetration of predic

ALT Analog in-memory computing performs the matrix-vector multiplications of neural networks directly inside the memory array, which saves time and energy. But each memory cell stores only a few levels and is noisy, so one cell cannot hold a weight precisely. The standard fix is to split each weight across several cells, like digits of a number. The base of this split decides the trade-off: a large base gives fine resolution but amplifies the noise, and a base near one averages the noise but wastes resolution. The best-known prior analysis considers only the noise, and so it always picks a base of one. We propose a principled method that also accounts for the limited number of levels per cell. It gives the optimal base in closed form, from a single measurement of the device noise. On a device-physics simulator, the optimal split is 3.3 dB more accurate than the common base-16 split, and it beats equal splitting in end-application accuracy.

ALT Data movement between memory and processing units remains a major bottleneck in data-centric systems. Memristive Stateful Logic (SL) addresses this problem by performing Boolean operations directly on stored resistive states. However, arithmetic efficiency depends jointly on the device-supported logic primitive set, the dependency structure of the resulting operation sequence, and its mapping to datapath architectures. While prior designs typically optimize device, logic, and architecture layers separately, we jointly consider them to co-design a stateful adder. We experimentally demonstrate a mixed MAGIC and FELIX logic primitive set on printed Electrochemical Metallization (ECM) memristors and derive a full adder sequence optimized for inter-bit carry propagation. Mapping this sequence to bit-serial, bit-parallel, and bit-pipelined datapaths reduces the latter two to 2n+6 cycles for an n-bit addition. For 32-bit addition, this requires 60-88% fewer cycles than prior SL adders. Across

ALT Many important computational workloads are bound by the performance of the memory system that supplies data to conventional processors. Compute in Memory (CiM) promises to circumvent this bottleneck by performing the processing within the memory. Neural Networks are memory-bound, and a notable example of such is the Hopfield Network. This work explores the design space of non-volatile computing-in-memory (NV-CiM) architectures using an instruction-level simulator to evaluate application mappings and workload-driven architectural adaptations. The exploration examines the resulting design trade-offs and includes theoretical comparisons with representative CPU and GPU architectures.

ALT Equilibrium Propagation (EqProp) updates each synapse by comparing a local term at the free and nudged equilibria. Because these two values occur at different times, a physical implementation requires temporary local memory. We show that this memory can emerge from a two-timescale synaptic model in which neural and volatile synaptic dynamics are jointly derived from a single energy function. A volatile state w relaxes toward the product of the pre- and postsynaptic activities, while a non-volatile state M stores the learned parameter. At equilibrium, w equals the local term entering the EqProp update. Using its net change between phases implements phase-based EqProp, while transferring its successive changes during nudging yields continual EqProp, in which the temporal comparison is carried by the synaptic dynamics themselves. On MNIST with a single-hidden-layer network, the phase-based model reaches 2.01 ± 0.09% test error versus 2.00 ± 0.13% for standard EqProp, and the continual mod

ALT Compute-in-Memory (CiM) is an alternative computing paradigm that circumvents the memory bandwidth bottleneck. Variants utilizing non-volatile memory cells (NVCiM) to perform Boolean operations directly within memory arrays offer significant density and energy-efficiency advantages. Fully realizing this potential, however, requires NVCiM-specific compiler optimizations. In conventional digital NVCiM systems, an output cell must be written – or preset – to an operation-specific value before any Boolean operation can occur. Preset-induced extra writes can degrade energy efficiency and cell endurance, often to the point of negating CiM's efficiency gains. In this paper, we introduce PRIM (Preset Reduction In Memory), a compiler optimization framework tailored for digital NVCiM that effectively minimizes preset overhead without compromising computational accuracy or architectural complexity. Unlike existing optimization approaches, PRIM is not restricted to specific types of Boolean operat

ALT Decoding visual stimuli from the spiking activity of retinal ganglion cells (RGCs) informs both our understanding of the retinal code and the design of visual prostheses. Natural vision is dynamic, yet state-of-the-art decoders mostly reconstruct single frames with artificial neural networks that process dense, continuous-valued signals rather than the retina's sparse, asynchronous spikes. We asked whether dynamic scenes can be reconstructed and tracked entirely within the spike domain, and at what computational cost. We built an end-to-end spiking neural network (SNN) whose neurons integrate the recorded RGC spikes over time. Populations of up to 1836 RGCs were recorded ex vivo from mouse retina on high-density microelectrode arrays while flashed images, moving bars, drifting gratings and randomly moving handwritten digits were presented. For moving digits, one shared spiking encoder fed two readouts, one reconstructing the image and one decoding the digit's position. Compute energy w

ALT Four-level indium-gallium-zinc oxide (IGZO) 2T0C memory needs reliable state formation, sensing references, and a path from cell errors to digital weights. We analyze 107 measured DC transfer curves from 37 isolated IGZO transistors (W/L = 3/0.5 micrometers). Four gate-bias operating points inferred from the first sweep are evaluated on later sweeps of 35 devices. Device-resolved operating points reduce second-sweep across-device current standard deviation by 49.4-52.4%, yet retaining initial thresholds increases misclassified points from 37/140 to 55/140. Leave-one-device-out reference estimation gives 0/140 on the second sweep; freezing second-sweep thresholds yields 6/140 on the third. Sampling eight reference transistors on the third sweep gives a mean held-out error fraction of 0.15% over 2,000 selections, versus 4.33% with frozen thresholds on matched held-out devices. We present conditional confusion matrices, a counterfactual common-gain sensitivity, and an INT4 error-propagati

ALT Use of carbon electrodes integrated with CMOS technology has great promise for lab-on-chip, biomedical, environmental, and industrial applications. One method of developing carbon electrodes is to 3D print polymer nanostructures on a CMOS chip, and use a thermal annealing process to pyrolyze them into carbon at high temperature, approximately 950 °C. Such high temperature is detrimental to the CMOS sensor circuits, causing severe degradation. We present a novel solution of localized Joule heating of these polymer nanostructures to achieve complete carbonization of the electrodes. Both analytical and COMSOL simulations guided the experiments to characterize the carbonization process conditions. Partial carbonization was achieved at 500-600 °C of global temperature, and complete carbonization was achieved by localized Joule heating. Pyrolized nanostructures monolithic samples on a silica wafer were fabricated using standard material processing, such as 2-Photon Polymerization. Pyrolysis

ALT Physical directional and quasi-omnidirectional antenna pairs are compared at 6.425–7.125 GHz over 32 position-matched indoor links per configuration: 23 line-of-sight (LOS) and nine non-LOS (NLOS) links in an open hall and an L-shaped corridor. Peak-gain normalization retains antenna-pattern weighting in the measured path loss, shadow-fading residuals, RMS delay spread (DS), and PDP-equivalent K factor. Hall LOS close-in exponents are nearly identical at 2.10/2.11 for directionalash quasi-omnidirectional pairs, yet median DS values differ markedly at 1.78/36.52 ns. Directional DS is lower at all LOS positions, with smaller fitted shadow-fading residuals and higher K factors. Representative PDPs associate these differences with reduced off-axis delayed energy. In corridor NLOS, the directional floating-intercept slope is negative, consistent with distance-dependent antenna-pattern weighting under the fixed pointing rule, whereas the quasi-omnidirectional slope is positive and DS orderin

ALT Proteinoid microspheres are electrically active assemblies of thermally polymerised amino acids that exhibit spontaneous oscillations, spike-like events, stimulus-dependent responses, adaptation and collective dynamics. We formulate these observations as an applied-mathematical problem and develop a unified dynamical framework for information processing in proteinoid networks. Individual microspheres are represented by nonlinear excitable or oscillatory systems, whereas interactions are described by weighted adaptive graphs and, in the spatial limit, reaction–diffusion dynamics. The framework combines signal propagation, attenuation, fading memory, adaptive coupling, synchronisation, information transfer, reservoir readout, robustness and energetic constraints. We define a task-relative proteinoid intelligence functional from normalised measures of stimulus information, memory, adaptation, directed information transfer, task performance and robustness, penalised by energetic and struct