Most of this is true but we should add some color to the last point … the industry has largely solved the smaller die problem by developing stitching (Intel) & bigger masks as an answer (TSM).
Intel 18A also already uses high NA heavily according to Intel & its used in the core ultra series 3 processors and D0 already within high volume manufacturing ranges. Stitching has already been extremely derisked with the XT260 system as well (I’m the guy who derisked it lol). The bigger mask work being done by TSM is an alternative but it’s a huge change and is projected to reach production by 2033 with all kinds of other complexity (the whole stage needs to be changed) 💀💀💀
Stitching on the other hand should be good enough for volume production by 2027 at earliest, again it’s been derisked technically a lot (I actually was the person who wrote the RTL for the stage & alignment so i would know lmao). People forget when I was first buying Intel hand over fist it was because I knew the advantage of high na and after the innovations lately it’s only become strongerrrr. Packaging was a sweetener ontop and I’m still in the minority here of betting on foundry turn around.
I don’t just say this just as an Intel shareholder but just as an engineer in general. I honestly think TSMC’s conservative culture and lack of innovation is going to be their downfall. Waiting for 2033 to adopt high NA EUV is going to be the fucking knife through their heart, CoWoS & CoPoS was already a fucking dumpster fire that TSMC is just throwing up their hands and letting the OSATs deal with it.
Rarely do I have this much of an information edge over investors lol. Today I had a great meeting with an investment firm who said they only hold TSM and never bought Intel and they said they just don’t see good ROIC on Intel fab. They did say though that if we thought there were technical reasons that wasn’t going to continue that’s a valid reason to own it.
Let me say this clearly: There are technical reasons as to why the ROI will improve a lot.
I didn’t put all my net worth into Intel 2 years ago for fun lol. I know what’s going on here better than most…
This is not true
TSMC will introduce its version of Backside Power called Super Power Rail (SPR) with the A16 node, which will enter risk production soon.
It's also more advanced than Intel's PowerVia, as TSMC directly connects the backside power to the transistors, while Intel's PowerVia uses nano TSVs to connect backside power to the transistors.
Intel will transition to a similar architecture in 2028 with the 14A node called PowerDirect.
TSMC isn't using High NA for 2-3 reasons. Multi-patterned Low-NA EUV will remain cheaper compared to High NA. The ecosystem around High NA is also not mature. TSMC doesn't want to commit a lot of CAPEX and waste cleanroom space to help mature it rn.
Third, and most importantly, the reticle field size of High NA is half (26 x 16.5mm) compared to Low NA (26 x 33mm). So the size of the monolithic die that u can print in a single exposure is halved (429 mm² vs 858 mm²). So u need to use reticle stitching to print a larger monolithic die with High NA.