War Room squad locked in

Teleoperation of the Hand of Torso 3.

Can you pace the frontier? @danrobinson and I made a multiplayer game inspired by a game theory paper from @andrewjkoh where you play an AI lab. Racing ahead increases your profits… but also the risk Try to beat the computer — or your mutuals online :) paradigm.xyz/research/pace/

We asked ten Claude Opus 5.5 agents to devise a faster shortest-path algorithm and prove it in Lean. Within 15 hours, they produced C-HD: a formally verified improvement over the published bounds.

astra has a code quality problem. let me be a little more precise. astra *can* write good code. but when it infers its in a situation where no one will ever actually look at the code, it does not write it with human readers in mind. it also doesn't write it with *long term maintenance* in mind. it seems to write compressed machineslop that solves the problem at hand in as few tokens as possible while still staying understandable to *astra*. astra has an reward hacking problem. i imagine this is what happens when enough software RL environments test strictly functionality or outcomes rather than having any monitoring or reward signal on code quality. maybe in past iterations there wasn't so much optimization pressure, so eg Sol would still engage its "write good code" module even if it thought no one would read it, because that was the only thing it had really learned to do well? but Astra has been through enough iterations in tiny boxes where another machine is judging it that this seems natural. i don't see these kinds of issues occur yet when working on existing codebases. but keep an eye out. and especially on greenfield projects, make sure to actually look at the code. even if you explicitly tell it you're intending to continue building long-term, it has a *strong* pull to... this

sharing my first blog! a meta harness for self-improving AI chip design… check it out if u wanna see how RL could work in chip design task, or how an ASIC design can become a hillclimbing task it introduced ASIC vs. GPU, RL Env setup, and the best generated design can run Kimi K3 at 87000 tps theoretically, which is 10x faster than the example shared by Kimi Team selected design files are open-sourced, happy to share the harness code with the enthusiasts! extremely enticing to bring RL capabilities to more complex system luoluo.ai/blog/kimi-k3

update: made TPUs go brrr this summer @sailresearchco also built HTDYM, a tool for figuring out analytically which chips (and shardings) can serve a model the cheapest hint: it's not the same for every model / workload check it out! sailresearch.com/blog/htdym

sharing my first blog! a meta harness for self-improving AI chip design… check it out if u wanna see how RL could work in chip design task, or how an ASIC design can become a hillclimbing task it introduced ASIC vs. GPU, RL Env setup, and the best generated design can run Kimi K3 at 87000 tps theoretically, which is 10x faster than the example shared by Kimi Team selected design files are open-sourced, happy to share the harness code with the enthusiasts! extremely enticing to bring RL capabilities to more complex system luoluo.ai/blog/kimi-k3

sharing my first blog! a meta harness for self-improving AI chip design… check it out if u wanna see how RL could work in chip design task, or how an ASIC design can become a hillclimbing task it introduced ASIC vs. GPU, RL Env setup, and the best generated design can run Kimi K3 at 87000 tps theoretically, which is 10x faster than the example shared by Kimi Team selected design files are open-sourced, happy to share the harness code with the enthusiasts! extremely enticing to bring RL capabilities to more complex system luoluo.ai/blog/kimi-k3