Author, Consultant. Computer Graphics, Embedded Systems, Photography. Founded @electronutLabs Currently writing a book on WebGPU.
Bengaluru, India
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The Humble iCE kit is shaping up. The FPGA board is ready for production, and the PMODs are getting there...🙂
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Wow! Here's the CERN news about this detector, with a link to the paper:
home.cern/aegis-transforms-s…
The AEgIS experiment at CERNs Antimatter Factory uses 60 IMX686 CMOS sensors to maybe see a moiré pattern in antiatoms after passing through gratings. The tinfoil-hat-crowd will love the PCB design 👁️
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Mahesh Venkitachalam retweeted
I will talk only to someone at PCB Power who has the authority to make real changes. Generic feedback to customer service will do little to solve systemic issues.
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Mahesh Venkitachalam retweeted
Please reduce the bureaucracy at PCB Power. Very difficult to get a project done. I request you to be more active on X - please connect with Indian makers and understand their needs.
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Met with a representative of PCB Power - hopefully they will do more to support makers in India. I hope to manufacture Humble iCE sold in India locally.
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Humble iCE (@latticesemi iCE40UP5k budget FPGA board) is production-ready. I am putting together a kit and something else as well. Stay tuned! 🙂
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Generating VGA signals might be regarded as the "Hello World" for FPGAs. Here, images are read into the block RAM of Humble iCE (iCE40UP5k) FPGA for the tiled background and the bouncing sprite.
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Google’s Tensor Processing Unit (TPU) uses the systolic array architecture - an idea from 1978 - to accelerate matrix multiplication with far less memory movement. Fun to build a small scale version on an FPGA. Links to original paper and TPU design:
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H. T. Kung and Charles E. Leiserson published the first paper describing systolic arrays in 1979. PDF:
eecs.harvard.edu/htk/static/…
TPU Architecture:
docs.cloud.google.com/tpu/do…
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For the curious, the chip is MSPM0C1104. Block diagram:
Texas Instruments has released a microcontroller measuring just 1.38 mm² — small enough to sit comfortably on a fingertip — at a unit price of around 20 cents. The chip is designed for ultra-low-power applications including medical wearables, hearables, and compact IoT devices, where both size and cost are critical constraints. At this scale, integrating processing capability into disposable or implantable medical devices becomes economically viable for the first time. TI positions the design as one of the smallest MCUs available in mass production today.
#TinyTech #Microcontroller #Innovation #EmbeddedWorld #TI #Wearables
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generate/for is an example of a commonly used Verilog construct. Unlike a software loop, it runs at elaboration (compile) time - the loop in this case instantiates three I2S stereo receivers, reading data from 6 mics concurrently on an FPGA.
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One of the aha moments I went through with Verilog HDL is that you're not writing a program, but describing a circuit. Took me time to develop intuition about what hardware my code was synthesising to on FPGA. Here's a classic example with blocking vs. non-blocking assignments:
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