Four that wanna own me/ Two that wanna stone me/ One says she’s a friend of mine

todays target is a baby camera asked DeepSeek to root it, de-bloat it, and cut it off from the cloud. it verified the whole thing across two reboots finally I can delete the app thats filled with ads

Wow 🤩 The whale 🐳 isn’t just shipping highly efficient, affordable frontier models - they’re open-sourcing the production inference stack that actually serves them at scale. DeepInfer (Apache 2.0) powers DeepSeek-V4.1-Flash w the same high-th/put, low-latency runtime used in production. It includes optimized kernels, Attention DP / balanced CP, MoE EP + EPLB, DSpark speculative decoding w confidence-scheduled verification, SWA bounded replay (to cut prefill work), 0-overhead asynchronous scheduling, batch-invariant inference, deterministic sampling, + structured outputs. Offline inference examples run from local Hugging Face checkpoints w no network required once the weights are cached. They also open-sourced deepseek-recipe, the production tokenizer/encoding path so community deployments match official API behavior. Open models + open kernels + open production inference. That’s a meaningfully different trajectory the whale 🐳 is offering to the world. I freakin love these guys 💙🥹💙

Bro, no. That stuff is a scaffold that elevates you to places you could never reach without.

When our AI code reviewer's cost per run doubled, we dug into the token usage to find out why. Learn how we used prompt caching and intelligent model routing to slash our inference bill by 68% while speeding up reviews. cfl.re/4isj2NU

Legends of the skies.

RCE in Discord 👀 bugcrowd.com/disclosures/638…

INSANE. An internal Anthropic research model's chain of thought after cracking the 26-year-old NSA elliptic curve seed mystery in under 30 minutes: 'Hmm wait. Let me be skeptical: am I in some sort of simulated/test environment? ... All top bits clear - 20 bits, chance 1e-6. So indeed real-world. Wow, it's a real discovery.'

The following ISA/CPU properties are all independent: - load–store vs. register–memory architecture - fixed width vs. variable width instruction encoding - hardwired vs. microcoded implementation - few vs. many instructions - simpler vs. complex instructions - simple vs. complex addressing modes - weak vs. strong memory ordering - delayed vs. non-delayed branching - windowed vs. flat register file - register-rich vs. register-poor - three-operand vs. two-operand instructions - zero register vs. no zero register - link-register-based vs. stack-based return addresses The properties on the left are historically associated with RISC, while the ones on the right are historically associated with CISC, but they really are independent. Back in the 80s, designing processors based on the properties on the left was advantageous because one could make a faster CPUs at a cheaper cost (at least for the manufacturer, not necessarily for the end user). Back in the late 80s/early 90s, RISC vs. CISC was associated with: - low transistor count vs. high-transistor count - high frequency vs. low frequency Notice how nowadays this association has completely dissapeared. High-performance CPU design can afford bigger transistor budgets and most of the performance of a modern CPU comes from properties completely orthogonal to the ones above.